Patent Document 1 describes a conventional method of achieving convergence of a hold time error. FIG. 19 is a diagram illustrating a principle of a method of achieving convergence of a hold time error described in Patent Document 1. FIG. 19 is essentially identical to FIG. 1 of Patent Document 1.
The method is applicable to a typical logic circuit that operates in synchronization with a clock signal and comprises a sequential circuit that operates in synchronization with a clock signal and a combinational circuit, wherein the combinational circuit (LOGIC, AND) is arranged between an output terminal (FF1Q, FF3Q) of a sequential circuit at a previous stage and an input terminal (FF2D, FF4D) of a sequential circuit at a next stage.
According to Patent Document 1, through step S101 in (A) of FIG. 19, obtain a hold time violation value for each path and obtain setup margin values for all paths irrespective whether a hold time error occurs or not (See (C) of FIG. 19, where Th denotes a hold time violation value and Ts denotes a setup margin value).
If a measure for the violation can be taken (step S106), a minimum setup margin value at an input/output terminal of almost all circuits is obtained. Each path which passes through an input/output terminal has its setup margin value. A minimum setup margin value for the input/output terminal means the minimum value of the setup margin values (see S102, (D) of FIG. 19, where Tsm denotes a minimum setup margin value, Ep denotes a count of hold time violation, FFPATH denotes a path which passes thorough the terminal).
Determine where a delay element is inserted based on data shown in the above (C) and (D) of FIG. 19 (S103) in order to achieve convergence of a hold time error, and insert a delay element (S104). Since data shown in (C) and (D) of FIG. 19 varies owing to insertion of a delay element, the data is updated (S105). According to Patent Document 1, continue the series of operations as long as a measure for the violation can be taken.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P2004-38383A